View LC865520B_275756.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : ENN*6697
CMOS IC
LC865520B/16B/12B/08B/04B
8-Bit Single Chip Microcontroller with On-Chip 20/16/12/08/04K-Byte ROM and 512-Byte RAM
Preliminary Overview
The LC865520B/16B/12B/08B/04B are 8-bit single chip microcontrollers with the following one-chip features: - CPU : Operable at a minimum bus cycle time of 0.5s - On-chip ROM Capacity : 20K/16K/12K/8K/4K bytes - On-chip RAM Capacity : 512 bytes (LC865520B/16B/12B/08B/04B) - 16-bit timer/counter (can be divided into two 8 bit timers) - 16-bit timer/PWM (can be divided into two 8 bit timers) - 8-channel x 8-bit AD converter - Two 8-bit synchronous serial-interface circuits - 13-source 10-vectored interrupt system
Features
(1) Read Only Memory (ROM) : LC865520B : LC865516B : LC865512B : LC865508B : LC865504B 20480 x 8 bits 16384 x 8 bits 12288 x 8 bits 8192 x 8 bits 4096 x 8 bits 512 x 8 bits
(2) Random Access Memory (RAM) : LC865520B/16B/12B/08B/04B
(3) Bus Cycle Time/Instruction Cycle Time The LC865520B/16B/12B/08B/04B are constructed to read ROM twice within one instruction cycle. It has 1.7 times the performance capability for the same instruction cycle compared to our 4-bit microcontrollers (LC66000 series). Bus cycle time indicates the speed to read ROM.
Bus cycle time Instruction cycle time Clock divider System clock oscillation Oscillation Frequency Ceramic (CF) Ceramic (CF) Internal RC Crystal (XTAL) 6MHz 3MHz 800kHz 32.768kHz Voltage 4.5V to 6.0V 2.5V to 6.0V 2.5V to 6.0V 2.5V to 6.0V
0.5s 2s 7.5s 183s
1s 4s 15s 366s
1/1 1/2 1/2 1/2
Ver.1.02 32300
11901 RM (IM) Chigira No.6697-1/21
LC865520B/16B/12B/08B/04B (4) Ports - Input/output ports : 3 ports (16 terminals : port 1,7,8) Input/output programmable for each bit individually - Maximum 15V withstand tolerance input/output port : 2 ports (15 terminals) Input/output programmable in nibble units : 1 port (8 terminals : port 0) (When the N-channel open drain output is selected, input/output can be specified by bit.) Input/output programmable for each bit individually : 1 port (7 terminals : port 3) - Input ports : 2 ports (6 terminals : port 7,8) (5) AD converter - 8-channel x 8-bit AD converter (6) Serial interface - 1 channel x 16-bit serial interface (8-bit transmission available by program) - 1 channel x 8-bit serial interface LSB first/MSB first-function available - An internal 8-bit baud-rate generator is common to both serial-interface circuits. (7) Timer - Timer 0 16-bit timer/counter 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with programmable prescaler Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with programmable prescaler Mode 3 : 16-bit counter The resolution of Timer is tCYC. (tCYC: cycle time) - Timer 1 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable-bit PWM (9-16bits) In Mode 0 and Mode 1, the resolution of Timer and PWM is tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM is selectable by program: tCYC or 1/2 tCYC. - Base timer Generates an overflow every 500ms for a clock application (using 32.768kHz crystal oscillation for the base timer oscillator). Generates an overflow every 976s, 3.9ms, 15.6ms or 62.5ms (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock, or programmable prescaler output of Timer 0. (8) Buzzer output - Built-in 4KHz and 2KHz buzzer generation function (using 32.768kHz crystal oscillation for the base timer oscillator) (9) Remote receiver circuit (share with P73/INT3/T0IN terminal) - Noise Rejection function (The filtering time of the noise rejection filter (1tCYC/16tCYC/64tCYC) can be switched by program.) (tCYC: instruction-cycle-time) - Polarity switch function (10) Watchdog timer - External RC circuit is required. - Interrupt or system reset is activated when the timer overflows.
No.6697-2/21
LC865520B/16B/12B/08B/04B (11) Interrupt - 13-source and 10-vectored interrupt function: 1. External interrupt INT0 (including watchdog timer) 2. External interrupt INT1 3. External interrupt INT2, Timer/counter T0L (lower 8 bits of Timer 0) 4. External interrupt INT3, Base timer 5. Timer/counter T0H (upper 8 bits of Timer 0) 6. Timer T1L (lower 8 bits of Timer 1), Timer T1H (upper 8 bits of Timer 1) 7. Serial interface SIO0 8. Serial interface SIO1 9. AD converter 10. Port 0 - Built-in Interrupt Priority control register Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority level can be assigned to the 11 interrupt sources of interrupts 3 to 10 shown above by the interrupt priority control register. For the external interrupt INT0 and INT1(interrupt 1 and 2), low or highest can be set regardless of the interrupt priority register. (12) Sub-routine stack levels - A maximum of 128 levels (set stack inside RAM) (13) Multiplication and division 16 bits x 8-bit (7 instruction-cycle-times) 16 bits / 8-bit (7 instruction-cycle-times) (14) 3 types of oscillation circuits - Built-in RC oscillation circuit used for the system clock. - CF oscillation circuit used for the system clock. - Crystal oscillation circuit used for the system clock and the time-base clock. (15) Standby function - HALT mode The HALT mode stops the program execution, which minimizes power consumption. This operation mode can be released by a system reset or an interrupt request. - HOLD mode The HOLD mode stops all oscillation circuits: CF, RC and Crystal oscillations. This mode can be released by the following conditions. * Feed "L" level to the reset terminal ( RES ) * Feed the selected level to P70/INT0, P71/INT1 terminals * Feed "L" level to the Port 0 (16) Shipping form * DIP42S * QIP48E (17) Development tools Evaluation (EVA) chip EPROM version One time version Emulator
: : : :
LC866096 LC86E5420 LC86P5420 EVA-86000 + ECB867100 (Evaluation chip board) + POD865400 (POD)
No.6697-3/21
LC865520B/16B/12B/08B/04B
Notice for use
1. The following must be taken into consideration by the user:
Notes Oscillation frequency range for system clock. Supply voltage range Clock Divider
15kHz to 30kHz 30kHz to 6MHz 15kHz to 30kHz 30kHz to 1.5MHz 1.5MHz to 3MHz Internal RC oscillation
4.5V to 6.0V 2.5V to 6.0V
4.5V to 6.0V 2.5V to 6.0V
1/1 1/1,1/2 1/1 1/1,1/2 1/2 1/1,1/2 1/2
Can not use 1/2 divider Can not use 1/2 divider Can not use 1/1 divider Can not use 1/1 divider
No.6697-4/21
LC865520B/16B/12B/08B/04B
Pin Assignment
*DIP42S
P00 P01 P02 P03 P04 P05 P06 P07 P70/INT0 RES XT1/P74 XT2/P75 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P17/PWM0 P16/BUZ P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P36 P35 P34 P33 P32 P31 P30 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P87/AN7 P86/AN6 P85/AN5
Package Dimension (unit : mm)
3025B
SANYO : DIP-42S(600mil)
No.6697-5/21
LC865520B/16B/12B/08B/04B
Pin Assignment
*QIP48E
P12/SCK0 P11/SI0/SB0 P10/SO0 P36 P35 P34 P33 NC P32 P31 P30 P73/INT3/T0IN P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM0 NC P00 P01 P02 P03 P04 NC 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12
37 38 39 40 41 42 43 44 45 46 47 48
NC P72/INT2/T0IN P71/INT1 P87/AN7 P86/AN6 P85/AN5 NC P84/AN4 P83/AN3 P82/AN2 P81/AN1 P80/AN0
P05 P06 P07 P70/INT0 RES XT1/P74 NC XT2/P75 VSS CF1 CF2 VDD
*Leave NC pins open.
Package Dimension (unit : mm)
3156
SANYO : QIP-48E
No.6697-6/21
LC865520B/16B/12B/08B/04B
System Block Diagram
Interrupt Control
IR
PLA
Stand-by Control
ROM
RC X'tal
Clock Generator
CR
PC
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
Port 8 ALU
Timer 1
Port 3
ADC
PSW
INT0-3 Noise Rejection Filter
RAR
RAM
Stack Pointer
Port 0
Watch Dog Timer
No.6697-7/21
LC865520B/16B/12B/08B/04B
Pin description
Name VSS VDD PORT0 P00 to P07 I/O I/O Function description Power terminal (-) Power terminal (+) * 8-bit input/output port * Port 0 interrupt input * Data direction programmable in nibble units * HOLD release input * A withstand tolerance of 15V when selecting N-channel open drain output * 8-bit input/output port * Data direction programmable for each bit individually * Other functions P10 SIO0 data output P11 SIO0 data input, bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input, bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM0 output) * 7-bit input/output port * Data direction programmable for each bit individually * A withstand tolerance of 15V when selecting N-channel open drain output Option * Pull-up resistor : Provided/Not provided (specified in nibble units) * Output form : CMOS/N-channel open drain (specified by bit) * Output form : CMOS/N-channel open drain (specified by bit)
PORT1 P10 to P17
I/O
PORT3 P30 to P36
I/O
* Pull-up resistor : Provided/Not provided (specified by bit) * Output form : CMOS/N-channel open drain (specified by bit)
PORT7
P70 to P73
P74, P75
* 4-bit input/output port * Data direction programmable for each bit individually * 2-bit input port * Other functions I/O P70 : INT0 input/HOLD release input/N-ch Tr. output for watchdog timer I P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input P74 : Input terminal XT1 for 32.768kHz X'tal oscillation P75 : Output terminal XT2 for 32.768kHz X'tal oscillation * Interrupt detection style, vector address Rising Falling Rising/ H level L level Vector Falling INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH
Continue.
No.6697-8/21
LC865520B/16B/12B/08B/04B
Name PORT8 P80 to 83 P84 to 87 I/O I I/O Function description * 4-bit input port * Data direction programmable for each bit individually * 4-bit input/output port * Other function AD converter input port (8 pins) Reset * Input terminal for 32.768kHz X'tal oscillation * Other function XT1 : Input port P74 * When not in use, connect terminal to VDD * Output terminal for 32.768kHz X'tal oscillation * Other function XT2 : Input port P75 * When not in use - If set as port, connect terminal to VDD. - If set as oscillation, leave terminal open. Input terminal for ceramic resonator Output terminal for ceramic resonator Option -
RES XT1/P74
I I
-
XT2/P75
O
-
CF1 CF2
I O
-
* All port options (except pull-up resistor of port 0) can be specified by bit.
A state of port terminals at reset
Name Port 0 Ports 1,3 Input/output mode Input Input Style of pull-up resistors when pull-up option is enabled Fixed pull-up resistor OFF Programmable pull-up resistor OFF
No.6697-9/21
LC865520B/16B/12B/08B/04B 1. Absolute Maximum Ratings at VSS=0V and Ta=25C
Ratings unit typ. max. V +7.0 VDD+0.3
Parameter Supply voltage Input voltage
Symbol
Pins VDD
Conditions
VDD[V]
Input/Output voltage
High level output current
Peak output current Total output current Peak output current Total output current
Low level output current
Maximum power consumption Operating temperature range Storage temperature range
VDDMAX VDD VI(1) * Ports 74,75 * Ports 80,81,82,83 * RES VIO(1) * Port 1 * Ports 70,71,72,73 * Ports 84,85,86,87 * Ports 0, 3 of CMOS output VIO(2) Ports 0, 3 of N-ch open drain output IOPH * Ports 0, 1, 3 * Ports 71,72,73 * Ports 84,85,86,87 IOAH(1) Ports 0, 1 IOAH(2) Port 3 IOAH(3) * Ports 71,72,73 * Ports 84,85,86,87 IOPL(1) Ports 0, 1, 3 IOPL(2) * Ports 70,71,72,73 * Ports 84,85,86,87 IOAL(1) Ports 0,1,70 IOAL(2) Port 3 IOAL(3) * Ports 71,72,73 * Ports 84,85,86,87 Pdmax(1) DIP42S Pdmax(2) QFP48E Topr
min. -0.3 -0.3
-0.3
VDD+0.3
-0.3 * CMOS output * For each pin Total of all pins Total of all pins Total of all pins For each pin For each pin Total of all pins Total of all pins Total of all pins Ta= -30 to+70C Ta= -30 to+70C -30 -10
15 mA
-30 -15 -10 20 15 60 40 20 630 350 70 mW C
Tstg
-55
125
No.6697-10/21
LC865520B/16B/12B/08B/04B 2. Recommended Operating Range at Ta=-30C to +70C, VSS=0V
Ratings typ.
Parameter Operating Supply voltage range Hold voltage
Symbol VDD(1) VDD(2) VHD VDD VDD
Pins
Conditions 0.98s tCYC 400s 3.9s tCYC 400s
VDD[V]
min. 4.5 2.5
max. 6.0 6.0
unit V
Input high voltage
VIH(1) VIH(2) VIH(3)
VIH(4) VIH(5)
VIH(6) VIH(7) Input low voltage VIL(1) VIL(2) VIL(3) VIL(4)
VIL(5) VIL(6) Operation tCYC cycle time Oscillation FmCF(1) frequency range (Note 1) FmCF(2)
FmRC FsXtal
RAM and register data 2.0 6.0 are kept in HOLD mode. Port 0 of CMOS output Output disable 2.5 to 6.0 0.33VDD VDD +1.0 Port 0 of N-ch open Output disable 4.0 to 6.0 0.75VDD 13.5 drain output 2.5 to 4.0 0.8VDD 13.5 * Port 1 Output disable 2.5 to 6.0 0.75VDD VDD * Ports 72,73 * Port 3 of CMOS output Port 3 of N-ch open Output disable 4.0 to 6.0 0.75VDD 13.5 drain output 2.5 to 4.0 0.8VDD 13.5 Output disable 2.5 to 6.0 0.75VDD VDD * Port 70 Port input/interrupt * Port 71 * RES Port 70 Output disable 2.5 to 6.0 0.9VDD VDD Watchdog timer * Port 8 * Output disable 2.5 to 6.0 0.75VDD VDD * Ports 74,75 * Using as port Port 0 of CMOS output Output disable 2.5 to 6.0 VSS 0.2VDD Port 0 of N-ch open Output disable 2.5 to 6.0 VSS 0.25VDD drain output * Ports 1,3 Output disable 2.5 to 6.0 VSS 0.25VDD * Ports 72,73 Output disable 2.5 to 6.0 VSS 0.25VDD * Port 70 Port input/interrupt * Port 71 * RES Port 70 Output disable 2.5 to 6.0 VSS 0.8VDD Watchdog timer to 1.0 * Port 8 * Output disable 2.5 to 6.0 VSS 0.25VDD * Ports 74,75 * Using as port 4.5 to 6.0 0.98 400 s 2.5 to 6.0 3.9 400 CF1, CF2 * 6MHz 4.5 to 6.0 5.88 6 6.12 MHz (ceramic resonator) * Refer to figure 1 CF1, CF2 *3MHz 2.5 to 6.0 2.94 3 3.06 (ceramic resonator) * Refer to figure 1 Internal RC oscillation 2.5 to 6.0 0.3 0.8 3.0 XT1, XT2 *32.768kHz 2.5 to 6.0 32.768 kHz (crystal oscillation) * Refer to figure 2
Continue.
No.6697-11/21
LC865520B/16B/12B/08B/04B
Ratings typ.
Parameter Oscillation stabilizing time (Note 1)
Symbol tmsCF(1)
Pins CF1, CF2
Conditions *6MHz (ceramic resonator) * Refer to figure 3 *3MHz (ceramic resonator) * Refer to figure 3 *32.768kHz (crystal oscillation) * Refer to figure 3
VDD[V] 4.5 to 6.0
min.
max.
unit ms
tmsCF(2)
CF1, CF2
4.5 to 6.0 2.5 to 6.0 4.5 to 6.0 2.5 to 6.0 s
tssXtal
XT1, XT2
(Note 1) The oscillation parameters are shown on table 1 and 2.
No.6697-12/21
LC865520B/16B/12B/08B/04B 3. Electrical Characteristics at Ta=-30C to +70C, VSS=0V
Ratings typ.
Parameter Input high current
Symbol IIH(1)
Pins Ports 0,3 of open drain output
Conditions * Output disable * VIN=13.5V (including the off-leak current of the output Tr.) * Output disable * Pull-up MOS Tr. OFF. * VIN=VDD (including the off-leak current of the output Tr.) VIN=VDD * VIN=VDD * Using as port * Output disable * Pull-up MOS Tr. OFF. * VIN=VSS (including the off-leak current of the output Tr.) VIN=VSS * VIN=VSS * Using as port IOH=-1.0mA IOH=-0.1mA IOL=10mA IOL=1.6mA * IOL=1.0mA * Every pin's IOL 1mA IOL=1.6mA * IOL=0.5mA * Every pin's IOL 1mA IOL=1mA * IOL=0.5mA * Every pin's IOL 1mA VOH=0.9VDD
VDD[V] 2.5 to 6.0
min.
max. 5
unit A
IIH(2)
* Port 0 without pull-up MOS Tr. * Ports 1,3 * Ports 70,71,72,73 * Port 8
RES
2.5 to 6.0
1
IIH(3) IIH(4) Input low current IIL(1)
Ports 74,75 * Ports 1,3 * Port 0 without pull-up MOS Tr. * Ports 70,71,72,73 * Port 8
RES
2.5 to 6.0 2.5 to 6.0 2.5 to 6.0 -1
1 1
IIL(2) IIL(3) Output high voltage
Ports 74,75
2.5 to 6.0 2.5 to 6.0
-1 -1 V
Output low voltage
VOH(1) * Ports 0,1,3 of CMOS output VOH(2) * Ports 71,72,73 * Ports 84,85,86,87 VOL(1) Ports 0,1,3 VOL(2) VOL(3) VOL(4) * Ports 71,72,73 VOL(5) * Ports 84,85,86,87 VOL(6) Port 70 VOL(7)
4.5 to 6.0 VDD-1 2.5 to 6.0 VDD-0.5 4.5 to 6.0 4.5 to 6.0 2.5 to 6.0 4.5 to 6.0 2.5 to 6.0 4.5 to 6.0 2.5 to 6.0 4.5 to 6.0 2.5 to 4.5 15 25 40 70
0.1VDD
1.5 0.4 0.4 0.4 0.4 0.4 0.4 70 150 V k
Pull-up MOS Rpu Tr. resistor Hysteresis voltage Pin capacitance VHIS
CP
* Ports 0,1,3 * Ports 70,71,72,73 * Ports 84,85,86,87 * Port 1 * Ports 70,71,72,73 * RES All pins
Output disable
2.5 to 6.0
* f=1MHz 2.5 to 6.0 * All pins except the measured terminal: VIN=VSS * Ta=25C
10
pF
No.6697-13/21
LC865520B/16B/12B/08B/04B 4. Serial Input/Output Characteristics at Ta=-30C to +70C, VSS=0V
Ratings typ.
Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Input clock
Symbol tCKCY(1) tCKL(1) tCKH(1) tCKCY(2) tCKL(2) tCKH(2) tICK
Pins SCK0,SCK1
Conditions Refer to figure 5
VDD[V] min. 2.5 to 6.0 2 1 1
max.
unit tCYC
Serial clock
Output clock
SCK0,SCK1
Serial input
Data set-up time Data hold time Output delay time (External clock used for serial transfer clock)
* SI0,SI1 * SB0,SB1
tCKI tCKO(1) * SO0,SO1 * SB0,SB1
* Use a 1k pullup resistor in the open drain output. * Refer to figure 5 * Data set-up to SCK0,1 * Data hold from SCK0,1 * Refer to figure 5 * Use a 1k pullup resistor in the open drain output. * Data hold from SCK0,1 * Refer to figure 5
2.5 to 6.0
2 1/2tCKCY 1/2tCKCY
4.5 to 6.0 2.5 to 6.0 4.5 to 6.0 2.5 to 6.0 4.5 to 6.0
0.1 0.4 0.1 0.4 7/12 tCYC
+0.2
s
Serial output
2.5 to 6.0
7/12 tCYC
+1
Output delay time (Internal clock used for serial transfer clock)
tCKO(2)
4.5 to 6.0
1/3 tCYC
+0.2
2.5 to 6.0
1/3 tCYC
+1
No.6697-14/21
LC865520B/16B/12B/08B/04B 5. Pulse Input Conditions at Ta=-30C to +70C, VSS=0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) Pins * INT0, INT1 * INT2/T0IN INT3/T0IN (The noise rejection clock is selected to 1/1.) INT3/T0IN (The noise rejection clock is selected to 1/16.) INT3/T0IN (The noise rejection clock is selected to 1/64.) Conditions * Interrupt acceptable * Timer0-countable * Interrupt acceptable * Timer0-countable * Interrupt acceptable * Timer0-countable * Interrupt acceptable * Timer0-countable Reset acceptable Ratings typ. max. unit tCYC
VDD[V] 2.5 to 6.0 2.5 to 6.0
min. 1 2
2.5 to 6.0
32
2.5 to 6.0
128 s
tPIL(5) RES
2.5 to 6.0
200
6. AD Converter Characteristics at Ta=-30C to + 70C, VSS=0V
Parameter Resolution Absolute precision (Note 2) Conversion time Symbol N ET tCAD AD conversion time = 16 x tCYC (ADCR2=0) (Note 3) AD conversion time = 32 x tCYC (if ADCR2=1) (Note 3) Analog input voltage range Analog port input current VAIN IAINH IAINL AN0 - AN7 VAIN=VDD VAIN=VSS Pins Conditions Ratings typ. 8 unit bit LSB s
VDD[V] 4.5 to 6.0
min.
max. 1.5
15.68 (tCYC= 0.98s) 31.36 (tCYC= 0.98s) VSS
65.28 (tCYC= 4.08s) 130.56 (tCYC= 4.08s) VDD 1
V A
-1
(Note 2) Absolute precision excludes the quantizing error (1/2 LSB). (Note 3) The conversion time is the time from executing the AD conversion instruction to setting the complete digital conversion value in the register.
No.6697-15/21
LC865520B/16B/12B/08B/04B 7. Sample Current Dissipation Characteristics at Ta=-30C to +70C, VSS=0V
Ratings typ. 12
Parameter Current drain during basic operation (Note 4)
Symbol IDDOP(1)
Pins VDD
Conditions * FmCF=6MHz by ceramic resonator * FsXtal=32.768kHz by crystal oscillation * System clock : CF oscillation (6MHZ) * Internal RC oscillation stops * 1/1 divided * FmCF=3MHz by ceramic resonator * FsXtal=32.768kHz by crystal oscillation * System clock : CF oscillation (3MHz) * Internal RC oscillation stops * 1/2 divided * FmCF=0Hz (when oscillation stops) * FsXtal=32.768kHz by crystal oscillation * System clock : RC oscillation * 1/2 divided * FmCF=0Hz (when oscillation stops) * FsXtal=32.768kHz by crystal oscillation * System clock : X'tal oscillation (32.768kHz) * Internal RC oscillation stops * 1/2 divided
VDD[V] 4.5 to 6.0
min.
max. 22
unit mA
IDDOP(2)
4.5 to 6.0
3
7
IDDOP(3)
2.5 to 4.5
2.0
5
IDDOP(4)
4.5 to 6.0
1.2
3
IDDOP(5) IDDOP(6)
2.5 to 4.5 4.5 to 6.0
1.0 35
2.5 130 A
IDDOP(7)
2.5 to 4.5
25
70
Continue.
No.6697-16/21
LC865520B/16B/12B/08B/04B
Ratings typ. 7
Parameter
Symbol
Pins
Conditions * HALT mode * FmCF=6MHz by ceramic resonator * FsXtal=32.768kHz by crystal oscillation * System clock : CF oscillation (6MHz) * Internal RC oscillation stops * 1/1 divided * HALT mode * FmCF=3MHz by ceramic resonator * FsXtal=32.768kHz by crystal oscillation * System clock : CF oscillation (3MHz) * Internal RC oscillation stops * 1/2 divided * HALT mode * FmCF=0Hz (when oscillation stops) * FsXtal=32.768kHz by crystal oscillation * System clock : RC oscillation *1/2 divided * HALT mode * FmCF=0Hz (when oscillation stops) * FsXtal=32.768kHz by crystal oscillation * System clock : X'tal oscillation (32.768kHz) * Internal RC oscillation stops * 1/2 divided HOLD mode
Current drain IDDHALT(1) VDD in HALT mode (Note 4)
VDD[V] 4.5 to 6.0
min.
Max. 12
unit mA
IDDHALT(2)
4.5 to 6.0
2.2
5
IDDHALT(3)
2.5 to 4.5
1.2
3
IDDHALT(4)
4.5 to 6.0
800
2000
A
IDDHALT(5)
2.5 to 4.5
500
1500
IDDHALT(6)
4.5 to 6.0
25
100
IDDHALT(7)
2.5 to 4.5
12
55
Current drain IDDHOLD(1) VDD in HOLD mode (Note 4) IDDHOLD(2)
4.5 to 6.0 2.5 to 4.5
0.06 0.02
30 20
(Note 4) The current of the output transistors and pull-up MOS transistors are excluded.
No.6697-17/21
LC865520B/16B/12B/08B/04B
Recommended Oscillation Circuit and Characteristics
The recommended circuit parameters are verified by an oscillator manufacturer using a SANYO provided oscillation evaluation board. Table 1. Recommended circuit parameters for the main system clock using the ceramic resonator
Frequency Manufacturer MURATA Oscillator CSA6.00MG CSTS0600MG03 CSA3.00MG CST3.00MGW Recommended circuit parameter C1 C2 Rd1 33pF 33pF 470 (15pF) (15pF) 470 33pF (30pF) 33pF (30pF) 470 470 Operating supply voltage range 4.5V to 6.0V 4.5V to 6.0V 2.5V to 6.0V 2.5V to 6.0V Note
6MHz
Internal C1, C2
3MHz
MURATA
Internal C1, C2
Table 2. Recommended circuit parameters for the sub system clock using the crystal oscillation
Frequency 32.768kHz Manufacturer SEIKO EPSON Oscillator MC-306 Recommended circuit parameter C3 18pF C4 18pF Rd2 560 Operating supply voltage range 2.5V to 6.0V Note
The recommended circuit parameter may vary according to the applications. For further assistance, please contact the oscillator manufacturer keeping the following in mind. !" Since the oscillation frequency precision is affected by the wiring capacitance of the application board, etc., is it required to adjust the oscillation frequency on the production board. !" The oscillation frequency and the recommended circuit parameter shown above apply when the operating temperature range is -30C to +70C. When using the clock oscillation circuit under the conditions which exceed the operating temperature range or in applications that require precision tolerances, please contact the oscillator manufacturer. !" using other circuit parameter than listed above, please contact SANYO. If Since the gain of oscillation circuit is reduced in order to minimize the power consumption of the circuit and the circuit can be affected by the noise, wiring capacity, etc., it is suggested to take the followings into consideration. !"The distance between the clock I/O terminals (XT1, XT2) and external parts should be as short as possible. !"The capacitors' (C1, C2) VSS should be placed close to the microcontroller's GND terminal and away from any other GND. !"The signal lines with large current or with rapid state changes should be placed away from the oscillation circuit.
CF1
CF2 Rd1
XT1
XT2 Rd2
CF C1 C2 C3
X'tal C4
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
No.6697-18/21
LC865520B/16B/12B/08B/04B
Power supply
Reset time
VDD VDD limit 0V
RES
RC oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Instruction execution OCR6=1
Operation mode
Unstable
Reset
Instruction execution

HOLD release signal
Valid
RC oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Instruction execution
(OCR6=1when entering HOLD) Figure 3 Oscillation stabilizing time
No.6697-19/21
LC865520B/16B/12B/08B/04B
VDD
RRES
RES CRES
(Note) Select CRES and RRES value to assure that at least 200s reset time is generated after the VDD becomes higher than the minimum operating voltage.
Figure 4
Reset circuit
0.5VDD
tCKCY tCKL SCK0 SCK1 tICK SI0 SI1 tCKO SO0, SO1 SB0, SB1 50pF tCKI tCKH
VDD
1k

Figure 5
Serial input / output test condition
tPIL
tPIH
Figure 6
Pulse input timing condition
No.6697-20/21
LC865520B/16B/12B/08B/04B memo:
PS No.6697-21/21

▲Up To Search▲

Price & Availability of LC865520B

	To Download LC865520B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .